As semiconductor fabrication technology advances, designers of integrated circuits and electronic circuits incorporating the same are able to integrate more and more functions into individual integrated circuit devices, or chips. As such, electronic circuits that once required several integrated circuits electrically coupled to one another on a circuit board or module may now be integrated into fewer integrated circuits, thereby increasing performance and reducing cost.
With increases in integrated circuit complexity, however, the processes of designing and testing integrated circuit designs become increasingly complex and time consuming. As a result, computers have become increasingly important in automating the design and testing of integrated circuits.
An important step in the development of a complex electronic system is that of verification, which may be used to verify the functional operation of a logic design for an integrated circuit. Traditionally, integrated circuits have been designed on a computer at a relatively high level of abstraction, typically in a hardware definition language such as VHDL or Verilog. Software tools, known as compilers, are then used to generate simulation models for the integrated circuits that can be executed on a logic simulator computer program to simulate the reactions of such circuits to various input conditions. By simulating the functional operation of an integrated circuit, potential errors or faulty logic can be identified and corrected in the high level logic design. Simulation is then rerun until the logic design functions as desired.
However, with the increasingly complex nature of many logic designs, software-based simulation is often too time consuming and inefficient. As a result, a significant amount of development effort has been directed toward hardware-based verification environments such as hardware-based logic simulators. Logic simulation of a logic design is often performed using a massively parallel hardware-based simulation accelerator incorporating hundreds or thousands of “logic processors” that are used to simulate, in hardware, the various functional components of a logic design. The logic processors can be specifically designed to efficiently simulate various functional components, and thus permit the simulation of potentially millions of logic gates in substantially less time than would be required for software-based simulation.
With a hardware-based simulation accelerator, a logic design to be simulated is typically in the form of a gate-level model that has been compiled from a high-level language. The compiled model breaks up each clock cycle (also referred to as an evaluation cycle) into a series of evaluation instructions or “steps”. The evaluation steps are typically executed in-order on each logic processor, and are repeated during each evaluation cycle.
One issue that arises in connection with some conventional hardware-based simulation accelerators is associated with the collection of simulation data during the simulation of a hardware design. For example, it may be desirable to collect a snapshot of a simulation at various points in time, or to check the status of certain data, prior to the completion of a simulation, particularly if the simulation is complex and expected to run for several hours. To this extent, some accelerator designs support the ability to store data in one or more memory arrays during a simulation, as well as the ability to access the memory arrays from outside an accelerator over an interface such as a service channel interface. Typically, the arrays are not primarily used for this purpose, but rather are principally used to simulate embedded arrays in a hardware design, or external arrays that may be accessed by a hardware design in normal usage.
By design, array accesses in an instruction-based hardware simulation accelerator typically need to be deterministic. Put another way, any access that is initiated in a given instruction is expected to be completed within a fixed number of cycles. Delays or interruptions as a result of external (i.e., service channel) accesses typically cannot be tolerated. As a result, in conventional accelerator designs providing external access capability, the only means of accessing these arrays from outside the simulator is to stop the simulation, perform the access(es), and then restart the simulation. Otherwise, a risk would exist that an external access to a memory array would prevent the completion of an internal array access within the designated number of cycles.
Stopping a simulation, however, adds overhead and reduces simulation efficiency, and is therefore undesirable. A significant need therefore continues to exist in the art for a manner of facilitating the performance of external array accesses in a hardware simulation accelerator with reduced impact on the execution of the accelerator.